Chip-Package Co-Design of a 4.7 GHz VCO

Future wireless communication applications require low-power and highly integrated transceiver solutions. The integration of the RF front-end poses a great challenge, in particular, as traditional implementations require a large number of external passive components. “Single-package” integration of complete transceivers based on an MCM-D technology with integrated passives is presented in this paper as a superior alternative to overcome the many problems of single-chip CMOS integration. Unloaded Qs of on-chip inductors are typically not higher than 5, which limits for example the phase noise performance of a VCO circuit. In this MCM-D technology, inductors with Qs higher than 50 are easily integrated. Active RF components can be assembled to the MCM substrate using Flip Chip technology. The parasitics introduced this way are much lower as compared to traditional chip bonding and packaging. To benefit from all the advantages offered by this approach, a careful co-design of ICs and passive components on the package is necessary. As an illustration, a 4.7 GHz VCO for a 5.2 GHz HIPERLAN-2 application is designed. The VCO consists of a core integrated in 0.35 μm BiCMOS technology and accompanying inductors for the resonator, which are integrated in the thin film MCM-D technology. This “single-package” solution results in a 5 dB phase noise reduction and at the same time the power consumption is lowered by almost a factor of 2 (18 mW to 9.5 mW) as compared to a single-chip design.